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TSMC’s CoWoS (Chip on Wafer on Substrate) packaging technology is designed to address the high computational power requirements of AI chips by utilizing 2.5D/3D packaging to enhance efficiency.
TSMC’s 2.5D CoWoS can be categorized into CoWoS-S, CoWoS-R, and CoWoS-L, with the differences lying in the materials used for the interposer and the HBM (High Bandwidth Memory) packaging capabilities.
Currently, the market mainstream is CoWoS-S, used in AI servers and high-performance computing products such as NVIDIA’s H100 and AMD’s MI300. However, its production cost is relatively high.
CoWoS-R uses InFO (Integrated Fan-Out) technology and organic interposers to replace the silicon interposers in CoWoS-S, integrating various SoCs and HBMs heterogeneously.
This reduces overall packaging costs, making it suitable for networking products.
CoWoS-L is TSMC’s latest technology, incorporating active components (LSI) in the silicon interposer, enhancing chip design and packaging flexibility.
It can stack up to 12 HBM3s at a lower cost than CoWoS-S and is expected to be introduced in 2024, potentially becoming the mainstream CoWoS technology for future AI chips.
CoWoS-S uses a single silicon interposer and through-silicon vias (TSVs) to achieve high-speed electrical signal transmission between the chip and the substrate.
However, single silicon interposers often face yield issues.
CoWoS-R employs InFO technology to replace the silicon interposer of CoWoS-S with an organic interposer.
This organic interposer has fine-pitch RDL (Redistribution Layer), providing high-speed connections between HBM and SoC chips or between chips and substrates.
The organic interposer’s flexibility, composed of polymers and copper wires, acts as a stress buffer, reducing reliability issues caused by the coefficient of thermal expansion mismatch between the substrate and the interposer.
CoWoS-R offers superior reliability and yield, allowing the new packaging to expand in size to meet more complex functional requirements.
CoWoS-L is a back-end chip packaging method within the CoWoS platform that combines the advantages of CoWoS-S and InFO technologies.
It uses an LSI (Local Silicon Interconnect) chip interposer to provide the most flexible integration, used for chip-to-chip interconnection and RDL layer power and signal transmission.
CoWoS-L retains the attractive features of CoWoS-S, such as TSVs, which reduce yield issues caused by large silicon interposers in CoWoS-S.
In certain practical cases, insulated vias (TIVs) may replace TSVs to reduce insertion loss.
This packaging starts with an interposer of 1.5 times the reticle size, configuring one SoC and four HBM blocks, and will further expand to larger sizes to integrate more chips.
TSMC is currently the only foundry capable of mass-producing interposers with line widths and pitches smaller than 1mm.
High-end AI servers, such as NVIDIA’s H100, A100, and AMD’s MI300, are limited by TSMC’s CoWoS capacity, with NVIDIA occupying most of the CoWoS capacity.
TSMC is continuously expanding related equipment, with a projected capacity of 28,000 wafers per month by Q4 2024 to meet the demand from NVIDIA and AMD.
CoWoS-R is a member of the advanced CoWoS packaging family, utilizing InFO technology with an RDL interposer for chip-to-chip interconnection, particularly in HBM and SoC heterogeneous integration.
CoWoS-L is a back-end chip packaging method within the CoWoS platform that combines the advantages of CoWoS-S and InFO technologies. It uses an LSI chip interposer to provide the most flexible integration for chip-to-chip interconnection and RDL layer power and signal transmission.